Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-18
Memory Optimization Using Prefetch
The Pentium 4 processor has two mechanisms for data prefetch:
software-controlled prefetch and an automatic hardware prefetch.
Software-controlled Prefetch
The software-controlled prefetch is enabled using the four prefetch
instructions introduced with Streaming SIMD Extensions instructions.
These instructions are hints to bring a cache line of data in to various
levels and modes in the cache hierarchy. The software-controlled
prefetch is not intended for prefetching code. Using it can incur
significant penalties on a multiprocessor system when code is shared.
Software prefetching has the following characteristics:
• Can handle irregular access patterns, which do not trigger the
hardware prefetcher.
• Can use less bus bandwidth than hardware prefetching; see below.
• Software prefetches must be added to new code, and do not benefit
existing applications.
Example 6-1 Pseudo-code for Using cflush
while (!buffer_ready} {}
mfence
for(i=0;i<num_cachelines;i+=cacheline_size) {
clflush (char *)((unsigned int)buffer + i)
}
mfence
prefnta buffer[0];
VAR = buffer[0];

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)