Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-9
Figure 3-1 Converting to Streaming SIMD Extensions Chart
OM15156
Code benefits
from SIMD
STOP
Identify Hot Spots in Code
Integer or
floating-point?
Yes
Floating Point
Why FP?
Can convert
to Integer?
Range or
Precision
If possible, re-arrange data
for SIMD efficiency
Integer
Change to use
SIMD Integer
Yes
Change to use
Single Precision
Can convert to
Single-precision?
Yes
No
No
Align data structures
Convert to code to use
SIMD Technologies
Follow general coding
guidelines and SIMD
coding guidelines
Use memory optimizations
and prefetch if appropriate
Schedule instructions to
optimize performance
No
Performance

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)