Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-12
Now for the case T
l
=18, T
b
=8 (2 cache lines are needed per iteration)
examine the following graph. Consider the graph of accesses per
iteration in example 1, Figure E-6.
The prefetch scheduling distance is a step function of T
c
, the
computation latency. The steady state iteration latency (il) is either
memory-bound or compute-bound depending on T
c
if prefetches are
scheduled effectively.
The graph in example 2 of accesses per iteration in Figure E-7 shows
the results for prefetching multiple cache lines per iteration. The cases
shown are for 2, 4, and 6 cache lines per iteration, resulting in differing
burst latencies. (T
l
= 18, T
b
= 8, 16, 24).
Figure E-6 Accesses per Iteration, Example 1

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)