Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-62
Underflow exceptions and denormalized source operands are usually
treated according to the IEEE 754 specification. If a programmer is
willing to trade pure IEEE 754 compliance for speed, two non-IEEE
754 compliant modes are provided to speed situations where underflows
and input are frequent: FTZ mode and DAZ mode.
When the FTZ mode is enabled, an underflow result is automatically
converted to a zero with the correct sign. Although this behavior is not
IEEE 754 compliant, it is provided for use in applications where
performance is more important than IEEE 754 compliance. Since
denormal results are not produced when the FTZ mode is enabled, the
only denormal floating-point numbers that can be encountered in FTZ
mode are the ones specified as constants (read only).
The DAZ mode is provided to handle denormal source operands
efficiently when running an SSE application. When the DAZ mode is
enabled, input denormals are treated as zeros with the same sign.
Enabling the DAZ mode is the way to deal with denormal floating-point
constants when performance is the objective.
If departing from IEEE 754 specification is acceptable and if
performance is critical, run SSE/SSE2/SSE3 applications with FTZ and
DAZ modes enabled.
Floating-point Modes
On the Pentium III processor, the FLDCW instruction is an expensive
operation. On the Pentium 4 processor,
FLDCW is improved for situations
where an application alternates between two constant values of the x87
NOTE. The DAZ mode is available with both the SSE
and SSE2 extensions, although the speed improvement
expected from this mode is fully realized only in SSE
code.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)