Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
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platform, software can extract information on the number and the
identities of each logical processor sharing that cache level and is made
available to application by the OS. This is discussed in detail in “Using
Shared Execution Resources in a Processor Core” in Chapter 7 and
Example 7-13.
Determine Prefetch Stride Using Deterministic Cache
Parameters
The prefetch stride provides the length of the region that the processor
will prefetch with the PREFETCHh instructions (PREFETCHT0,
PREFETCHT1, PREFETCHT2 and PREFETCHNTA). Software will
use this length as the stride when prefetching into a particular level of
the cache hierarchy as identified by the particular prefetch instruction
used. The prefetch size is relevant for cache types of Data Cache (1) and
Unified Cache (3) and should be ignored for other cache types. Software
should not assume that the coherency line size is the prefetch stride. If
this field is zero, then software should assume a default size of 64 bytes
is the prefetch stride. Software will use the following algorithm to
determine what prefetch size to use depending on whether the
deterministic cache parameter mechanism is supported or the legacy
mechanism.
• If a processor supports the deterministic cache parameters and
provides a non-zero prefetch size, then that prefetch size is used.
• If a processor supports the deterministic cache parameters and does
not provides a prefetch size then default size for each level of the
cache hierarchy is 64 bytes.
• If a processor does not support the deterministic cache parameters
but provides a legacy prefetch size descriptor (0xF0 - 64 byte, 0xF1
- 128 byte) will be the prefetch size for all levels of the cache
hierarchy.
• If a processor does not support the deterministic cache parameters
and does not provide a legacy prefetch size descriptor, then 32-bytes
is the default size for all levels of the cache hierarchy.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)