Intel ARCHITECTURE IA-32 User Manual

3-1
3
Coding for SIMD
Architectures
Intel Pentium 4, Intel Xeon and Pentium M processors include support
for Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions
technology (SSE), and MMX technology. In addition, Streaming SIMD
Extensions 3 (SSE3) were introduced with the Pentium 4 processor
supporting Hyper-Threading Technology at 90 nm technology. Intel
Core Solo and Intel Core Duo processors support SSE3/SSE2/SSE, and
MMX. These single-instruction, multiple-data (SIMD) technologies
enable the development of advanced multimedia, signal processing, and
modeling applications.
To take advantage of the performance opportunities presented by these
new capabilities, do the following:
• Ensure that the processor supports MMX technology, Streaming
SIMD Extensions, Streaming SIMD Extensions 2, and Streaming
SIMD Extensions 3.
• Ensure that the operating system supports MMX technology and
SSE (OS support for SSE2 and SSE3 is the same as OS support for
SSE).
• Employ all of the optimization and scheduling strategies described
in this book.
• Use stack and data alignment techniques to keep data properly
aligned for efficient memory use.
• Utilize the cacheability instructions offered by SSE and SSE2,
where appropriate.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)