Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-9
overhead when buffers are exchanged between the producer and
consumer. To achieve optimal scaling with the number of cores, the
synchronization overhead must be kept low. This can be done by
ensuring the producer and consumer threads have comparable time
constants for completing each incremental task prior to exchanging
buffers.
Example 7-1 illustrates the coding structure of single-threaded
execution of a sequence of task units, where each task unit (either the
producer or consumer) executes serially (shown in Figure 7-2). In the
equivalent scenario under multi-threaded execution, each
producer-consumer pair is wrapped as a thread function and two threads
can be scheduled on available processor resources simultaneously.
Example 7-1 Serial Execution of Producer and Consumer Work Items
for (i = 0; i < number_of_iterations; i++) {
producer (i, buff); // pass buffer index and buffer address
consumer (i, buff);
}(
Figure 7-2 Single-threaded Execution of Producer-consumer Threading Model
P(1)P(1) C(1)C(1)P(1)
Main
Thread

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)