Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-16
Move Byte Mask to Integer
The pmovmskb instruction returns a bit mask formed from the most
significant bits of each byte of its source operand. When used with the
64-bit MMX registers, this produces an 8-bit mask, zeroing out the
upper 24 bits in the destination register. When used with the 128-bit
XMM registers, it produces a 16-bit mask, zeroing out the upper 16 bits
in the destination register. The 64-bit version is shown in Figure 4-7 and
Example 4-10.
Example 4-9 Repeated pinsrw Instruction Code
; Input:
; edx pointer to structure containing source
; values at offsets: of +0, +10, +13, and +24
; immediate value: “1”
; Output:
; MMX register with new 16-bit value inserted
;
pxor mm0, mm0 ; Breaks dependedncy on previous value of mm0
mov eax, [edx]
pinsrw mm0, eax, 0
mov eax, [edx+10]
pinsrw mm0, eax, 1
mov eax, [edx+13]
pinsrw mm0, eax, 2
mov eax, [edx+24]
pinsrw mm0, eax, 3

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)