Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-10
The out-of-order core aggressively reorders µops so that µops whose
inputs are ready (and have execution resources available) can execute as
soon as possible. The core can issue multiple µops per cycle.
The retirement section ensures that the results of execution are
processed according to original program order and that the proper
architectural states are updated.
Figure 1-3 illustrates a diagram of the major functional blocks
associated with the Intel NetBurst microarchitecture pipeline. The
following subsections provide an overview for each.
Figure 1-3 The Intel NetBurst Microarchitecture
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Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)