Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-33
The main loop consists of two functions: transformation and lighting.
For each object, the main loop calls a transformation routine to update
some data, then calls the lighting routine to further work on the data. If
the size of array
v[Num] is larger than the cache, then the coordinates for
v[i] that were cached during Transform(v[i]) will be evicted from
the cache by the time we do
Lighting(v[i]). This means that v[i]
will have to be fetched from main memory a second time, reducing
performance.
for (i=0; i<Num; i++) {
Lighting(v[i]);
}
....
}
Example 3-19 Strip Mined Code
main()
{
Vertex_rec v[Num];
....
for (i=0; i < Num; i+=strip_size) {
for (j=i; j < min(Num, i+strip_size); j++) {
Transform(v[j]);
}
for (j=i; j < min(Num, i+strip_size); j++) {
Lighting(v[j]);
}
}
}
Example 3-18 Pseudo-code Before Strip Mining (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)