Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-32
Mix Software Prefetch with Computation Instructions
It may seem convenient to cluster all of the prefetch instructions at the
beginning of a loop body or before a loop, but this can lead to severe
performance degradation. In order to achieve best possible performance,
prefetch instructions must be interspersed with other computational
instructions in the instruction sequence rather than clustered together. If
possible, they should also be placed apart from loads. This improves the
instruction level parallelism and reduces the potential instruction
resource stalls. In addition, this mixing reduces the pressure on the
memory access resources and in turn reduces the possibility of the
prefetch retiring without fetching data.
Example 6-6 illustrates distributing prefetch instructions. A simple and
useful heuristic of prefetch spreading for a Pentium 4 processor is to
insert a prefetch instruction every 20 to 25 clocks. Rearranging prefetch
instructions could yield a noticeable speedup for the code which stresses
the cache resource.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)