Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-95
User/Source Coding Rule 19. (M impact, ML generality) Avoid the use of
conditional branches inside loops and consider using SSE instructions to
eliminate branches.
User/Source Coding Rule 20. (M impact, ML generality) Keep induction
(loop) variables expressions simple.
Miscellaneous
This section explains separate guidelines that do not belong to any
category described above.
NOPs
Code generators generate a no-operation (NOP) to align instructions.
The NOPs are recommended for the following operations:
• 1-byte: xchg EAX, EAX
• 2-byte: mov reg, reg
• 3-byte: lea reg, 0 (reg) (8-bit displacement)
• 6-byte: lea reg, 0 (reg) (32-bit displacement)
These are all true NOPs, having no effect on the state of the machine
except to advance the EIP. Because NOPs require hardware resources to
decode and execute, use the least number of NOPs to achieve the
desired padding.
The one byte NOP,
xchg EAX,EAX, has special hardware support.
Although it still consumes a
μop and its accompanying resources, the
dependence upon the old value of
EAX is removed. Therefore, this μop
can be executed at the earliest possible opportunity, reducing the
number of outstanding instructions. This is the lowest cost NOP
possible.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)