Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
A-4
default, and targets the Intel Pentium 4 processor and subsequent
processors. Code produced will run on any Intel architecture 32-bit
processor, but will be optimized specifically for the targeted processor.
Automatic Processor Dispatch Support
(-Qx[extensions] and -Qax[extensions])
The -Qx[extensions] and -Qax[extensions] options provide
support to generate code that is specific to processor-instruction
extensions. The corresponding options on Linux are -x[extensions] and
-ax[extensions].
-Qx[extensions] generates specialized code to run exclusively on
the processors indicated by the extension(s).
-Qax[extensions] generates code specialized to processors which
support the specified extensions, but also
generates generic IA-32 code. The generic code
usually executes slower than the specialized
version. A runtime check for the processor type
is made to determine which code executes.
You can specify the same extensions for either option as follows:
i Pentium II and Pentium III processors, which use the
CMOV and FCMOV instructions.
M Pentium processor with MMX technology, Pentium II,
and Pentium III processors.
K Streaming SIMD Extensions. Includes the i and M
extensions.
W Streaming SIMD Extensions 2. Includes the i, M,
and K extensions.
B Streaming SIMD Extensions 2 and optimizations for
the Intel Pentium M processor. Includes the
i, M,
K,k
and W extensions.
P Streaming SIMD Extensions 3. Includes the i, M, K,
and W extensions.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)