Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
9-4
ACPI C-States
When computational demands are less than 100%, part of the time the
processor is doing useful work and the rest of the time it is idle. For
example, the processor could be waiting on an application time-out set
by a Sleep() function, waiting for a web server response, or waiting for a
user mouse click. Figure 9-2 illustrates the relationship between active
and idle time.
When an application moves to a wait state, the OS issues a HLT
instruction and the processor enters a halted state in which it waits for
the next interrupt. The interrupt may be a timer interrupt that comes
every 10 ms or an interrupt that signals an event.
As shown in the illustration of Figure 9-2, the processor is in either
active or idle (halted) state. ACPI defines four C-state types (C0, C1, C2
and C3). Processor-specific C states of an IA-32 processor can be
mapped to an ACPI C-state type via ACPI standard mechanisms. The
C-state types are divided into two categories: active (C0), in which the
processor consumes full power; and idle (C1-3), in which the processor
is idle and may consume significantly less power.
Figure 9-2 Active Time Versus Halted Time of a Processor

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)