Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-5
The index of a C-state type designates the depth of sleep. Higher
numbers indicate a deeper sleep state and lower power consumption.
They also require more time to wake up (higher exit latency).
C-state types are described below:
• C0: The processor is active and performing computations and
executing instructions.
• C1: This is the lowest-latency idle state, which has very low exit
latency. In the C1 power state, the processor is able to maintain the
context of the system caches.
• C2: This level has improved power savings over the C1 state. The
main improvements are provided at the platform level.
• C3: This level provides greater power savings than C1 or C2. In C3,
the processor stops clock generating and snooping activity. It also
allows system memory to enter self-refresh mode.
The basic technique to implement OS power management policy to
reduce static power consumption is by evaluating processor idle
durations and initiating transitions to higher-numbered C-state types.
This is similar to the technique of reducing active power consumption
by evaluating processor utilization and initiating P-state transitions. The
OS looks at history within a time window and then sets a target C-state
type for the next time window, as illustrated in Figure 9-3:

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)