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Intel ARCHITECTURE IA-32 - Page 419

Intel ARCHITECTURE IA-32
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Power Optimization for Mobile Usages 9
9-5
The index of a C-state type designates the depth of sleep. Higher
numbers indicate a deeper sleep state and lower power consumption.
They also require more time to wake up (higher exit latency).
C-state types are described below:
C0: The processor is active and performing computations and
executing instructions.
C1: This is the lowest-latency idle state, which has very low exit
latency. In the C1 power state, the processor is able to maintain the
context of the system caches.
C2: This level has improved power savings over the C1 state. The
main improvements are provided at the platform level.
C3: This level provides greater power savings than C1 or C2. In C3,
the processor stops clock generating and snooping activity. It also
allows system memory to enter self-refresh mode.
The basic technique to implement OS power management policy to
reduce static power consumption is by evaluating processor idle
durations and initiating transitions to higher-numbered C-state types.
This is similar to the technique of reducing active power consumption
by evaluating processor utilization and initiating P-state transitions. The
OS looks at history within a time window and then sets a target C-state
type for the next time window, as illustrated in Figure 9-3:

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