Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
A-20
Intel
®
Software College
The Intel
®
Software College is a valuable resource for classes on
Streaming SIMD Extensions 2 (SSE2), Threading and the IA-32 Intel
Architecture. For online training on how to use the SSE2 and
Hyper-Threading Technology, refer to the IA-32 Architecture Training -
Online Training at
http://developer.intel.com/software/college/CourseCatalog.asp?CatID=
web-based. For key algorithms and their optimization examples for the
Pentium 4 processor, refer to the application notes. You can find
additional information on classroom training from the Intel Software
College Web site at http://developer.intel.com/software/college
, and
general information for developers from Intel Developer Services at
http://www.intel.com/ids
.
Figure A-3 Intel Thread Profiler Can Show Critical Paths of Threaded Execution
Timelines

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)