Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-12
The execution trace cache and the translation engine have cooperating
branch prediction hardware. Branch targets are predicted based on their
linear address using branch prediction logic and fetched as soon as
possible. Branch targets are fetched from the execution trace cache if
they are cached, otherwise they are fetched from the memory hierarchy.
The translation engine’s branch prediction information is used to form
traces along the most likely paths.
The Out-of-order Core
The core’s ability to execute instructions out of order is a key factor in
enabling parallelism. This feature enables the processor to reorder
instructions so that if one µop is delayed while waiting for data or a
contended resource, other µops that appear later in the program order
may proceed. This implies that when one portion of the pipeline
experiences a delay, the delay may be covered by other operations
executing in parallel or by the execution of µops queued up in a buffer.
The core is designed to facilitate parallel execution. It can dispatch up to
six µops per cycle through the issue ports (Figure 1-4, page 19). Note
that six µops per cycle exceeds the trace cache and retirement µop
bandwidth. The higher bandwidth in the core allows for peak bursts of
greater than three µops and to achieve higher issue rates by allowing
greater flexibility in issuing µops to different execution ports.
Most core execution units can start executing a new µop every cycle, so
several instructions can be in flight at one time in each pipeline. A
number of arithmetic logical unit (ALU) instructions can start at two per
cycle; many floating-point instructions start one every two cycles.
Finally, µops can begin execution out of program order, as soon as their
data inputs are ready and resources are available.
Retirement
The retirement section receives the results of the executed µops from the
execution core and processes the results so that the architectural state is
updated according to the original program order. For semantically

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)