Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Floating-point Applications 5
5-7
To utilize all 4 computation slots, the vertex data can be reorganized to
allow computation on each component of 4 separate vertices, that is,
processing multiple vectors simultaneously. This can also be referred to
as an SoA form of representing vertices data shown in Table 5-1.
Organizing data in this manner yields a unique result for each
computational slot for each arithmetic operation.
Vertical computation takes advantage of the inherent parallelism in 3D
geometry processing of vertices. It assigns the computation of four
vertices to the four compute slots of the Pentium III processor, thereby
eliminating the disadvantages of the horizontal approach described
earlier (using SSE alone). The dot product operation implements the
SoA representation of vertices data. A schematic representation of dot
product operation is shown in Figure 5-2.
Table 5-1 SoA Form of Representing Vertices Data
Vx array X1 X2 X3 X4 ..... Xn
Vy array Y1 Y2 Y3 Y4 ..... Yn
Vz array Z1 Z2 Z3 Y4 ..... Zn
Vw array W1 W2 W3 W4 ..... Wn

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)