Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-24
Absolute Difference of Signed Numbers
Chapter 4 computes the absolute difference of two signed numbers.
The technique used here is to first sort the corresponding elements of the
input operands into packed words of the maximum values, and packed
words of the minimum values. Then the minimum values are subtracted
from the maximum values to generate the required absolute difference.
The key is a fast sorting technique that uses the fact that
B = xor(A,
xor (A,B)) and A = xor(A,0). Thus in a packed data type, having
some elements being
xor(A,B) and some being 0, you could xor such
an operand with
A and receive in some places values of A and in some
values of
B. The following examples assume a packed-word data type,
each element being a signed value.
NOTE. There is no MMX™ technology subtract
instruction that receives
SIGNED operands and
subtracts them with UNSIGNED saturation.
Example 4-17 Absolute Difference of Signed Numbers
;Input:
; MM0 signed source operand
; MM1 signed source operand
;Output:
; MM0 absolute difference of the unsigned
; operands
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)