Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-44
Per-thread Stack Offset
To prevent private stack accesses in concurrent threads from thrashing
the first-level data cache, an application can use a per-thread stack offset
for each of its threads. The size of these offsets should be multiples of a
common base offset. The optimum choice of this common base offset
may depend on the memory access characteristics of the threads; but it
should be multiples of 128 bytes.
One effective technique for choosing a per-thread stack offset in an
application is to add an equal amount of stack offset each time a new
thread is created in a thread pool.
7
Example 7-9 shows a code fragment
that implements per-thread stack offset for three threads using a
reference offset of 1024 bytes.
User/Source Coding Rule 35. (H impact, M generality) Adjust the private
stack of each thread in an application so that the spacing between these stacks
is not offset by multiples of 64 KB or 1 MB to prevent unnecessary cache line
evictions (when using IA-32 processors supporting Hyper-Threading
Technology).
7. For parallel applications written to run with OpenMP, the OpenMP runtime library in
Intel KAP/Pro Toolset automatically provides the stack offset adjustment for each thread.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)