Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-34
The size and alignment restrictions for store forwarding are illustrated in
Figure 2-2.
Coding rules to help programmers satisfy size and alignment restrictions
for store forwarding follow.
Assembly/Compiler Coding Rule 18. (H impact, M generality) A load that
forwards from a store must have the same address start point and therefore the
same alignment as the store data.
Assembly/Compiler Coding Rule 19. (H impact, M generality) The data of
a load which is forwarded from a store must be completely contained within the
store data.
Figure 2-2 Size and Alignment Restrictions in Store Forwarding
OM15155
(a) Small load after
Large Store
Store
Load
Load Aligned with
Store Will Forward
Non-Forwarding
Penalty
(b) Size of Load >=
Store
Store
Load
Penalty
(c) Size of Load >=
Store(s)
Store
Load
Penalty
(d) 128-bit Forward
Must Be 16-Byte
Aligned
Store
Load
Penalty
16-Byte
Boundary

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)