Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
1-41
Figure 1-7 Pentium D Processor, Pentium Processor Extreme Edition
and Intel Core Duo Processor
System Bus
Architectual State
Execution Engine
Local APIC Local APIC
Execution Engine
Architectual State
Bus Interface Bus Interface
Pentium D Processor
Caches Caches
System Bus
Architectual
State
Execution Engine
Local APIC Local APIC
Execution Engine
Architectual
State
Bus Interface Bus Interface
Local APIC Local APIC
Architectual
State
Architectual
State
Pentium Processor Extreme Edition
Caches
Caches
System Bus
Architectual State
Execution Engine
Local APIC Local APIC
Execution Engine
Architectual State
Bus Interface
Intel Core Duo Processor
Second Level Cache

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)