Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-14
Transparent Cache-Parameter Strategy
If CPUID instruction supports function leaf 4, also known as
deterministic cache parameter leaf, this function leaf will report detailed
cache parameters for each level of the cache hierarchy in a deterministic
and forward-compatible manner across current and future IA-32
processor families. See CPUID instruction in the IA-32 Intel®
Architecture Software Developer’s Manual, Volume 2B.
For coding techniques that rely on specific parameters of a cache level,
using the deterministic cache parameter allow software to implement
such coding technique to be forward-compatible with future generations
of IA-32 processors, and be cross-compatible with processors equipped
with different cache sizes.
Threading Strategy and Hardware Multi-Threading Support
Current IA-32 processor families offer hardware multi-threading
support in two forms: dual-core technology and Hyper-Threading
Technology. Future trend for IA-32 processors will continue to improve
in the direction of multi-core technology.
To fully harness the performance potentials of the hardware
multi-threading capabilities in current and future generations of IA-32
processors, software must embrace a threaded approach in application
design. At the same time, to address the widest range of installed base of
machines, multi-threaded software should be able to run without failure
on single processor without hardware multi-threading support, and
multi-threaded software implementation should also achieve
comparable performance on a single logical processor relative to an
unthreaded implementation if such comparison can be made. This
generally requires architecting a multi-threaded application to minimize
the overhead of thread synchronization. Additional software
optimization guidelines on multi-threading are discussed in Chapter 7.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)