Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-9
Figure 4-2 illustrates two values interleaved in the destination register,
and Example 4-4 shows code that uses the operation. The two signed
doublewords are used as source operands and the result is interleaved
signed words. The pack instructions can be performed with or without
saturation as needed.
Figure 4-1 PACKSSDW mm, mm/mm64 Instruction Example
Figure 4-2 Interleaved Pack with Saturation
OM15159
D C B A
D
1
C
1
B
1
A
1
mm/m64 mm
mm
OM15160
D C B A
D
1
B
1
C
1
A
1
MM/M64 mm
mm

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)