Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-31
The subtraction operation presented above is an absolute difference, that
is,
t = abs(x-y). The byte values are stored in temporary space, all
values are summed together, and the result is written into the lower
word of the destination register.
Packed Average (Byte/Word)
The pavgb and pavgw instructions add the unsigned data elements of the
source operand to the unsigned data elements of the destination register,
along with a carry-in. The results of the addition are then each
independently shifted to the right by one bit position. The high order
bits of each element are filled with the carry bits of the corresponding
sum.
The destination operand is an SIMD register. The source operand can
either be an SIMD register or a memory operand.
Figure 4-9 PSADBW Instruction Example
OM15167
MM/m64
X8 X7 X6 X5 X4 X3 X2 X1
063
MM
Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
063
Temp
T8 T7 T6 T5 T4 T3 T2 T1
063
========
--------
MM
0..0 0..0 0..0 T1+T2+T3+T4+T5+T6+T7+T8
063

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)