IA-32 Intel® Architecture Optimization
B-56
Using Performance Events of Intel Core Solo and
Intel Core Duo processors
There are performance events specific to the microarchitecture of Intel
Core Solo and Intel Core Duo processors (see Table A-9 of the IA-32
Intel® Architecture Software Developer’s Manual, Volume 3B).
Understanding the Results in a Performance Counter
Each performance event detects a well-defined microarchitectural
condition occurring in the core while the core is active. A core is active
when:
• It is running code (excluding the halt instruction).
• It is being snooped by the other core or a logical processor on the
platform. Note that this can happen when the core is halted.
Some microarchitectural conditions are applicable to a sub-system
shared by more than one core; and some performance events provide an
event mask (or unit mask) that allows qualification at the physical
processor boundary or at bus agent boundary.
Some events allow qualifications that permit the counting of
microarchitectural conditions associated with a particular core versus
counts from all cores in a physical processor (see L2 and bus related
events in Table A-9 of the IA-32 Intel® Architecture Software
Developer’s Manual, Volume 3B).
When a multi-threaded workload does not use all cores continuously, a
performance counter counting a core-specific condition may progress to
some extent on the halted core and stop progressing; or a unit mask may
be qualified to continue counting occurrences of the condition attributed
to either processor core. Typically, one can adjust the highest two bits
(bits 15:14 of the IA32_PERFEVTSELx MSR) in the unit mask field to
distinguish such asymmetry (See Section 18.12 of the same reference
above).
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