Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
C-14
Table C-5 Streaming SIMD Extension 64-bit Integer Instructions
Instruction Latency
1
Throughput Execution Unit
CPUID 0F3n 0F2n 0x69n 0F3n 0F2n 0x69n 0F2n
PAVGB/PAVGW mm, mm 2 2 1 1 MMX_ALU
PEXTRW r32, mm, imm8 7 7 2 2 2 1 MMX_SHFT,
FP_MISC
PINSRW mm, r32, imm8 4 4 1 1 1 1 MMX_SHFT,
MMX_MISC
PMAX mm, mm 2 2 1 1 MMX_ALU
PMIN mm, mm 2 2 1 1 MMX_ALU
PMOVMSKB
3
r32, mm 771221FP_MISC
PMULHUW
3
mm, mm 98 11 FP_MUL
PSADBW mm, mm 4 4 5 1 1 2 MMX_ALU
PSHUFW mm, mm, imm8 2 2 1 1 1 1 MMX_SHFT
See “Table Footnotes”
Table C-6 MMX Technology 64-bit Instructions
Instruction Latency
1
Throughput Execution Unit
2
CPUID 0F3n 0F2n 0x69n 0f3n 0F2n 0x69n 0F2n
MOVD mm, r32 2 2 1 1 MMX_ALU
MOVD
3
r32, mm 55 11 FP_MISC
MOVQ mm, mm 6 6 1 1 FP_MOV
PACKSSWB/PACKSSD
W/PACKUSWB mm, mm
22 11 MMX_SHFT
PADDB/PADDW/PADDD
mm, mm
22 11 MMX_ALU
PAD DS B/PA DD S W
/PADDUSB/PADDUSW
mm, mm
22 11 MMX_ALU
PAND mm, mm 2 2 1 1 MMX_ALU
PANDN mm, mm 2 2 1 1 MMX_ALU
PCMPEQB/PCMPEQD
PCMPEQW mm, mm
22 11 MMX_ALU
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)