Intel ARCHITECTURE IA-32 - Page 529

IA-32 Instruction Latency and Throughput C
C-15
PCMPGTB/PCMPGTD/
PCMPGTW mm, mm
22 11 MMX_ALU
PMADDWD
3
mm, mm 98 11 FP_MUL
PMULHW/PMULLW
3
mm, mm
98 11 FP_MUL
POR mm, mm 2 2 1 1 MMX_ALU
PSLLQ/PSLLW/
PSLLD mm, mm/imm8
22 11 MMX_SHFT
PSRAW/PSRAD mm,
mm/imm8
22 11 MMX_SHFT
PSRLQ/PSRLW/PSRLD
mm, mm/imm8
22 11 MMX_SHFT
PSUBB/PSUBW/PSUBD
mm, mm
22 11 MMX_ALU
PSUBSB/PSUBSW/PSU
BUSB/PSUBUSW mm,
mm
22 11 MMX_ALU
PUNPCKHBW/PUNPCK
HWD/PUNPCKHDQ
mm, mm
22 11 MMX_SHFT
PUNPCKLBW/PUNPCK
LWD/PUNPCKLDQ mm,
mm
22 11 MMX_SHFT
PXOR mm, mm 2 2 1 1 MMX_ALU
EMMS
1
12 12
See “Table Footnotes”
Table C-6 MMX Technology 64-bit Instructions (continued)
Instruction Latency
1
Throughput Execution Unit
2