Intel ARCHITECTURE IA-32 User Manual

IA-32 Instruction Latency and Throughput C
C-15
PCMPGTB/PCMPGTD/
PCMPGTW mm, mm
22 11 MMX_ALU
PMADDWD
3
mm, mm 98 11 FP_MUL
PMULHW/PMULLW
3
mm, mm
98 11 FP_MUL
POR mm, mm 2 2 1 1 MMX_ALU
PSLLQ/PSLLW/
PSLLD mm, mm/imm8
22 11 MMX_SHFT
PSRAW/PSRAD mm,
mm/imm8
22 11 MMX_SHFT
PSRLQ/PSRLW/PSRLD
mm, mm/imm8
22 11 MMX_SHFT
PSUBB/PSUBW/PSUBD
mm, mm
22 11 MMX_ALU
PSUBSB/PSUBSW/PSU
BUSB/PSUBUSW mm,
mm
22 11 MMX_ALU
PUNPCKHBW/PUNPCK
HWD/PUNPCKHDQ
mm, mm
22 11 MMX_SHFT
PUNPCKLBW/PUNPCK
LWD/PUNPCKLDQ mm,
mm
22 11 MMX_SHFT
PXOR mm, mm 2 2 1 1 MMX_ALU
EMMS
1
12 12
See “Table Footnotes”
Table C-6 MMX Technology 64-bit Instructions (continued)
Instruction Latency
1
Throughput Execution Unit
2

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)