Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-32
The PAVGB instruction operates on packed unsigned bytes and the PAVGW
instruction operates on packed unsigned words.
Complex Multiply by a Constant
Complex multiplication is an operation which requires four
multiplications and two additions. This is exactly how the
pmaddwd
instruction operates. In order to use this instruction, you need to format
the data into multiple 16-bit values. The real and imaginary components
should be 16-bits each. Consider Example 4-23, which assumes that the
64-bit MMX registers are being used:
• Let the input data be Dr and Di where Dr is real component of the
data and
Di is imaginary component of the data.
• Format the constant complex coefficients in memory as four 16-bit
values [
Cr -Ci Ci Cr]. Remember to load the values into the MMX
register using a
movq instruction.
• The real component of the complex product is
Pr = Dr*Cr - Di*Ci
and the imaginary component of the complex product is
Pi = Dr*Ci + Di*Cr.
Example 4-23 Complex Multiply by a Constant
; Input:
; MM0 complex value, Dr, Di
; MM1 constant complex coefficient in the form
; [Cr -Ci Ci Cr]
; Output:
; MM0 two 32-bit dwords containing [Pr Pi]
;
punpckldq MM0, MM0 ; makes [Dr Di Dr Di]
pmaddwd MM0, MM1 ; done, the result is
; [(Dr*Cr-Di*Ci)(Dr*Ci+Di*Cr)]

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)