Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-2
Intel Core Solo and Intel Core Duo processors incorporate
microarchitectural enhancements for performance and power efficiency
that are in addition to those introduced in the Pentium M processor.
SIMD Technology
SIMD computations (see Figure 1-1) were introduced in the IA-32
architecture with MMX technology. MMX technology allows SIMD
computations to be performed on packed byte, word, and doubleword
integers. The integers are contained in a set of eight 64-bit registers
called MMX registers (see Figure 1-2).
The Pentium III processor extended the SIMD computation model with
the introduction of the Streaming SIMD Extensions (SSE). SSE allows
SIMD computations to be performed on operands that contain four
packed single-precision floating-point data elements. The operands can
be in memory or in a set of eight 128-bit XMM registers (see Figure
1-2). SSE also extended SIMD computational capability by adding
additional 64-bit MMX instructions.
Figure 1-1 shows a typical SIMD computation. Two sets of four packed
data elements (X1, X2, X3, and X4, and Y1, Y2, Y3, and Y4) are
operated on in parallel, with the same operation being performed on

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)