Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-19
The caveat to this is that only certain types of loops can be automatically
vectorized, and in most cases user interaction with the compiler is
needed to fully enable this.
Example 3-12 shows the code for automatic vectorization for the simple
four-iteration loop (from Example 3-8).
Compile this code using the
-Qax and -Qrestrict switches of the Intel
C++ Compiler, version 4.0 or later.
The
restrict qualifier in the argument list is necessary to let the
compiler know that there are no other aliases to the memory to which
the pointers point. In other words, the pointer for which it is used,
provides the only means of accessing the memory in question in the
scope in which the pointers live. Without the restrict qualifier, the
compiler will still vectorize this loop using runtime data dependence
testing, where the generated code dynamically selects between
sequential or vector execution of the loop, based on overlap of the
parameters (See documentation for the Intel C++ Compiler). The
restrict keyword avoids the associated overhead altogether.
Refer to the Intel® C++ Compiler User’s Guide for details.
Example 3-12 Automatic Vectorization for a Simple Loop
void add (float *restrict a,
float *restrict b,
float *restrict c)
{
int i;
for (i = 0; i < 4; i++) {
c[i] = a[i] + b[i];
}
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)