Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-55
Characterization Metrics x87 Input Assists
x87 Output Assists
Machine Clear Count
Memory Order Machine Clear
Self-Modifying Code Clear
Scalar DP Retired
Scalar SP Retired
Packed DP Retired
Packed SP Retired
128-bit MMX Instructions Retired
64-bit MMX Instructions Retired
x87 Instructions Retired
Stalled Cycles of Store Buffer Resources
Stalls of Store Buffer Resources
1
Parallel counting is not supported due to ESCR restrictions.
Table B-7 Metrics That Are Independent of Logical Processors
General Metrics Non-Sleep Clockticks
TC and Front End Metrics Page Walk Miss ITLB
Memory Metrics Page Walk DTLB All Misses
All WCB Evictions
WCB Full Evictions
Bus Metrics Bus Data Ready from the Processor
Characterization Metrics SSE Input Assists
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)