Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-54
Bus Metrics Bus Accesses from the Processor
1
Non-prefetch Bus Accesses from the Processor
1
Reads from the Processor
1
Writes from the Processor
1
Reads Non-prefetch from the Processor
1
All WC from the Processor
1
All UC from the Processor
1
Bus Accesses from All Agents
1
Bus Accesses Underway from the processor
1
Bus Reads Underway from the processor
1
Non-prefetch Reads Underway from the processor
1
All UC Underway from the processor
1
All WC Underway from the processor
1
Bus Writes Underway from the processor
1
Bus Accesses Underway from All Agents
1
Write WC Full (BSQ)
1
Write WC Partial (BSQ)
1
Writes WB Full (BSQ)
1
Reads Non-prefetch Full (BSQ)
1
Reads Invalidate Full- RFO (BSQ)
1
UC Reads Chunk (BSQ)
1
UC Reads Chunk Split (BSQ)
1
UC Write Partial (BSQ)
1
IO Reads Chunk (BSQ)
1
IO Writes Chunk (BSQ)
1
WB Writes Full Underway (BSQ)
1
UC Reads Chunk Underway (BSQ)
1
Write WC Partial Underway(BSQ)
1
continued
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)