Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-80
Prefixes and Instruction Decoding
An IA-32 instruction can be up to 15 bytes in length. Prefixes can
change the length of an instruction that the decoder must recognize. In
some situations, using a length-changing prefix (LCP) causes extra
delay in decoding the instruction.
The prefixes that change the length of a instruction include
• Operand size prefix (0x66)
• Address size prefix (0x67)
Only in some situations does the use of a length-changing prefix
actually cause the length of an instruction to change (the prefix itself is
not considered as contributing to a change in instruction length in this
respect).
For example, the instruction “xor eax,0xffff” is encoded as (35 FF FF 00
00) in 32-bit code; while overriding the default operand size with 0x66
results in the instruction “xor ax,0xffff”, which is encoded as (66 35 FF
FF). Use of an LCP causes a change in the number of bytes to encode
the displacement operand in the instruction.
On Pentium M, Intel Core Solo and Intel Core Duo processors; the
following situation causes extra delays when decoding an instruction
with an LCP:
• Processing an instruction with its length affected by the presence of
a Length Changing Prefix (LCP)
Situations for which the presence of operand-size override prefix (0x66)
does not change the length of a instruction are:
• Processing an instruction in a subset which the 0x66 prefix does not
change instruction length. The instructions that may experience this
penalty include: neg, not, mul, imul, div, idiv, and test with the
opcode byte encoding of 0xF7.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)