Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-48
Front-end Optimization
In the Intel NetBurst microarchitecture family of processors, the
instructions are decoded into micro-ops (μops) and sequences of μops
(called traces) are stored in the Execution Trace Cache. The Trace
Cache is the primary sub-system in the front end of the processor that
delivers μop traces to the execution engine. Optimization guidelines for
front-end operation in single-threaded applications are discussed in
Chapter 2.
For dual-core processors where the second-level unified cache (for data
and code) is duplicated for each core (e.g., Pentium Processor Extreme
Edition, Pentium D processor), there are no special considerations for
front-end optimization on behalf of two processor cores in a physical
processor.
For dual-core processors where the second-level unified cache is shared
by two processor cores (e.g. Intel Core Duo processor), multi-threaded
software should consider the increase in code working set due to two
threads fetching code from the unified cache as part of front-end and
cache optimization.
This next two sub-sections discuss guidelines for optimizing the
operation of the Execution Trace Cache on IA-32 processors supporting
Hyper-Threading Technology.
Avoid Excessive Loop Unrolling
Unrolling loops can reduce the number of branches and improve the
branch predictability of application code. Loop unrolling is discussed in
detail in Chapter 2. Loop unrolling must be used judiciously. Be sure to
consider the benefit of improved branch predictability and the cost of
increased code size relative to the Trace Cache.
User/Source Coding Rule 37. (M impact, L generality) Avoid excessive loop
unrolling to ensure the Trace cache is operating efficiently.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)