Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-12
The other destination register will contain the opposite combination
illustrated in Figure 4-4.
Code in the Example 4-6 unpacks two packed-word sources in a
non-interleaved way. The goal is to use the instruction which unpacks
doublewords to a quadword, instead of using the instruction which
unpacks words to doublewords.
Figure 4-3 Result of Non-Interleaved Unpack Low in MM0
Figure 4-4 Result of Non-Interleaved Unpack High in MM1
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Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)