Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-46
Per-instance Stack Offset
Each instance an application runs in its own linear address space; but the
address layout of data for stack segments is identical for the both
instances. When the instances are running in lock step, stack accesses
are likely to cause of excessive evictions of cache lines in the first-level
data cache for some implementations of Hyper-Threading Technology
in IA-32 processors.
Although this situation (two copies of an application running in lock
step) is seldom an objective for multithreaded software or a
multiprocessor platform, it can happen by an end-user’s direction. One
solution is to allow application instance to add a suitable linear
address-offset for its stack. Once this offset is added at start-up, a buffer
of linear addresses is established even when two copies of the same
application are executing using two logical processors in the same
physical processor package. The space has negligible impact on running
dissimilar applications and on executing multiple copies of the same
application.
{ DWORD Stack_offset, ID_Thread1, ID_Thread2, ID_Thread3;
Stack_offset = 1024;
// Stack offset between parent thread and the first child thread.
ID_Thread1 = CreateThread(Func_thread_entry, &Stack_offset);
// Call OS thread API.
Stack_offset = 2048;
ID_Thread2 = CreateThread(Func_thread_entry, &Stack_offset);
Stack_offset = 3072;
ID_Thread3 = CreateThread(Func_thread_entry, &Stack_offset);
}
Example 7-9 Adding an Offset to the Stack Pointer of Three Threads (Contd.)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)