Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-53
User/Source Coding Rule 8. (H impact, H generality) To achieve effective
amortization of bus latency, software should pay attention to favor data access
patterns that result in higher concentrations of cache miss patterns with cache
miss strides that are significantly smaller than half of the hardware prefetch
trigger threshold.
Non-Temporal Store Bus Traffic
Peak system bus bandwidth is shared by several types of bus activities,
including: reads (from memory), read for ownership (of a cache line),
and writes. The data transfer rate for bus write transactions is higher if
64 bytes are written out to the bus at a time.
Typically, bus writes to Writeback (WB) type memory must share the
system bus bandwidth with read-for-ownership (RFO) traffic.
Non-temporal stores do not require RFO traffic; they do require care in
managing the access patterns in order to ensure 64 bytes are evicted at
once (rather than evicting several 8 byte chunks).
Although full 64-byte bus writes due to non-temporal stores have data
bandwidth that is twice that of bus writes to WB memory, transferring
8-byte chunks wastes bus request bandwidth and delivers significantly
lower data bandwidth.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)