Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-9
• GetActivePwrScheme: Retrieves the active power scheme (current
system power scheme) index. An application can use this API to
ensure that system is running best power scheme.Avoid Using Spin
Loops
Spin loops are used to wait for short intervals of time or for
synchronization. The main advantage of a spin loop is immediate
response time. Using the PeekMessage() in Windows API has the same
advantage for immediate response (but is rearely needed in current
multi-tasking operating systems).
However, spin loops and PeekMessage() in message loops require the
constant attention of the processor, preventing it from entering lower
power states. Use them sparingly and replace them with the appropriate
API when possible. For example:
• When an application needs to wait for more then a few milliseconds,
it should avoid using spin loops and use the Windows
synchronization APIs, such as WaitForSingleObject().
• When an immediate response is not necessary, an application should
avoid using PeekMessage(). Use WaitMessage() to suspend the
thread until a message is in the queue.
Intel
®
Mobile Platform Software Development Kit
5
provides a rich set
of APIs for mobile software to manage and optimize power
consumption of mobile processor and other components in the platform.
Reducing Amount of Work
When a processor is in the C0 state, the amount of energy a processor
consumes from the battery is proportional to the amount of time the
processor executes an active workload. The most obvious technique to
conserve power is to reduce the number of cycles it takes to complete a
5. Evaluation copy may be downloaded at
http://www.intel.com/cd/software/products/asmo-na/eng/219691.htm

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)