Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-4
SIMD improves the performance of 3D graphics, speech recognition,
image processing, scientific applications and applications that have the
following characteristics:
• inherently parallel
• recurring memory access patterns
• localized recurring operations performed on the data
• data-independent control flow
SIMD floating-point instructions fully support the IEEE Standard 754
for Binary Floating-Point Arithmetic. They are accessible from all
IA-32 execution modes: protected mode, real address mode, and Virtual
8086 mode.
SSE, SSE2, and MMX technologies are architectural extensions in the
IA-32 Intel architecture. Existing software will continue to run
correctly, without modification on IA-32 microprocessors that
incorporate these technologies. Existing software will also run correctly
in the presence of applications that incorporate SIMD technologies.
Figure 1-2 SIMD Instruction Register Usage
MM7
MM6
MM7
MM3
MM2
MM1
MM0
MM5
MM4
MM7
XMM6
XMM7
XMM3
XMM2
XMM1
XMM0
XMM5
XMM4
64-bit MMX Registers
128-bit XMM Registers
OM15149

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)