Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-13
Extract Word
The pextrw instruction takes the word in the designated MMX register
selected by the two least significant bits of the immediate value and
moves it to the lower half of a 32-bit integer register, see Figure 4-5 and
Example 4-7.
Example 4-6 Unpacking Two Packed-word Sources in a Non-interleaved Way
; Input:
; MM0 packed-word source value
; MM1 packed-word source value
; Output:
; MM0 contains the two low-end words of the
; original sources, non-interleaved
; MM2 contains the two high end words of the
; original sources, non-interleaved.
movq MM2, MM0 ; copy source1
punpckldq MM0, MM1 ; replace the two high-end words
; of MMO with two low-end words of
; MM1; leave the two low-end words
; of MM0 in place
punpckhdq MM2, MM1 ; move two high-end words of MM2
; to the two low-end words of MM2;
; place the two high-end words of
; MM1 in two high-end words of MM2

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)