Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-36
Example 2-14 illustrates a stalled store-forwarding situation that may
appear in compiler generated code. Sometimes a compiler generates
code similar to that shown in Example 2-14 to handle spilled byte to the
stack and convert the byte to an integer value.
Example 2-15 offers two alternatives to avoid the non-forwarding
situation shown in Example 2-14.
Example 2-13 A Non-forwarding Example of Large Load After Small Store
mov [EBP], ‘a’
mov [EBP + 1], ‘b’
mov [EBP + 2], ‘c’
mov [EBP + 3], ‘d’
mov EAX, [EBP] ; blocked
; The first 4 small store can be consolidated into
; a single DWORD store to prevent this non-forwarding
; situation
Example 2-14 A Non-forwarding Situation in Compiler Generated Code
mov DWORD PTR [esp+10h], 00000000h
mov BYTE PTR [esp+10h], bl
mov eax, DWORD PTR [esp+10h] ; Stall
and eax, 0xff ; converting back to byte value
Example 2-15 Two Examples to Avoid the Non-forwarding Situation in
Example 2-14
;A. Use movz instruction to avoid large load after small
; store, when spills are ignored
movz eax, bl ; Replaces the last three instructions
; in Example 2-12
;B. Use movz instruction and handle spills to the stack
mov DWORD PTR [esp+10h], 00000000h
mov BYTE PTR [esp+10h], bl
movz eax, BYTE PTR [esp+10h] ; not blocked

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)