Intel ARCHITECTURE IA-32 User Manual

Optimizing Cache Usage 6
6-35
In the temporally-adjacent scenario, subsequent passes use the same
data and find it already in second-level cache. Prefetch issues aside, this
is the preferred situation. In the temporally non-adjacent scenario, data
used in pass m is displaced by pass (m+1), requiring data re-fetch into
the
first level cache and perhaps the second level cache if a later pass
reuses the data. If both data sets fit into the second-level cache, load
operations in passes 3 and 4 become less expensive.
Figure 6-6 Cache Blocking – Temporally Adjacent and Non-adjacent Passes
Dataset A
Dataset B
Dataset B
Dataset A
Dataset A
Dataset A
Dataset B
Dataset B
Pass 1
Pass 2
Pass 3
Pass
4
Temporally
adjacent passes
Temporally
non-adjacent
passes

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)