Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-14
Tools for Creating Multithreaded Applications
Programming directly to a multithreading application programming
interface (API) is not the only method for creating multithreaded
applications. New tools such as the Intel
®
Compiler have become
available with capabilities that make the challenge of creating
multithreaded application easier.
Two features available in the latest Intel Compilers are:
• generating multithreaded code using OpenMP* directives
4
• generating multithreaded code automatically from unmodified
high-level code
5
Programming with OpenMP Directives. OpenMP provides a
standardized, non-proprietary, portable set of Fortran and C++ compiler
directives supporting shared memory parallelism in applications.
OpenMP supports directive-based processing. This uses special
preprocessors or modified compilers to interpret parallelism expressed
in Fortran comments or C/C++ pragmas. Benefits of directive-based
processing include:
• The original source can be compiled unmodified.
• It is possible to make incremental code changes. This preserves
algorithms in the original code and enables rapid debugging.
• Incremental code changes help programmers maintain serial
consistency. When the code is run on one processor, it gives the
same result as the unmodified source code.
• Offering directives to fine tune thread scheduling imbalance.
• Intel’s implementation of OpenMP runtime can add minimal
threading overhead relative to hand-coded multi-threading.
4. Intel Compiler 5.0 and later supports OpenMP directives. Visit
http://developer.intel.com/software/products for details.
5. Intel Compiler 6.0 supports auto-parallelization.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)