Intel ARCHITECTURE IA-32 User Manual

Multi-Core and Hyper-Threading Technology 7
7-15
Automatic Parallelization of Code. While OpenMP directives allow
programmers to quickly transform serial applications into parallel
applications, programmers must identify specific portions of the
application code that contain parallelism and add compiler directives.
Intel Compiler 6.0 supports a new (
-Qparallel) option, which can
identify loop structures that contain parallelism. During program
compilation, the compiler automatically attempts to decompose the
parallelism into threads for parallel processing. No other intervention or
programmer is needed.
Supporting Development Tools. The Intel
®
Threading Tools include
Intel
®
Thread Checker and Thread Profiler.
Intel
®
Thread Checker. Use Intel Thread Checker to find threading
errors (e.g. data races, stalls and deadlocks) and reduce the amount of
time spent debugging threaded applications.
Intel Thread Checker product is an Intel VTune Performance Analyzer
plug-in data collector that executes a program and automatically locates
threading errors. As the program runs, Intel Thread Checker monitors
memory accesses and other events and automatically detects situations
which could cause unpredictable threading-related results.
Thread Profiler. Thread Profiler is a plug-in data collector for the Intel
VTune Performance Analyzer. Use it to analyze threading performance
and identify parallel performance bottlenecks. It graphically illustrates
what each thread is doing at various levels of detail using a hierarchical
summary. It can identify inactive threads, critical paths and imbalances
in thread execution, etc. Data is collapsed into relevant summaries,
sorted to identify parallel regions or loops that require attention.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)