Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-6
SSE instructions are useful for 3D geometry, 3D rendering, speech
recognition, and video encoding and decoding.
Streaming SIMD Extensions 2
Streaming SIMD extensions 2 add the following:
• 128-bit data type with two packed double-precision floating-point
operands
• 128-bit data types for SIMD integer operation on 16-byte, 8-word,
4-doubleword, or 2-quadword integers
• support for SIMD arithmetic on 64-bit integer operands
• instructions for converting between new and existing data types
• extended support for data shuffling
• extended support for cacheability and memory ordering operations
SSE2 instructions are useful for 3D graphics, video decoding/encoding,
and encryption.
Streaming SIMD Extensions 3
Streaming SIMD extensions 3 add the following:
• SIMD floating-point instructions for asymmetric and horizontal
computation
• a special-purpose 128-bit load instruction to avoid cache line splits
• an x87 FPU instruction to convert to integer independent of the
floating-point control word (FCW)
• instructions to support thread synchronization
SSE3 instructions are useful for scientific, video and multi-threaded
applications.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)