Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-30
Unsigned Byte
The pmaxub instruction returns the maximum between the eight
unsigned bytes in either two SIMD registers, or one SIMD register and a
memory location.
The
pminub instruction returns the minimum between the eight
unsigned bytes in either two SIMD registers, or one SIMD register and a
memory location.
Packed Multiply High Unsigned
The pmulhuw and pmulhw instruction multiplies the unsigned/signed
words in the destination operand with the unsigned/signed words in the
source operand. The high-order 16 bits of the 32-bit intermediate results
are written to the destination operand.
Packed Sum of Absolute Differences
The psadbw instruction (see Figure 4-9) computes the absolute value of
the difference of unsigned bytes for either two SIMD registers, or one
SIMD register and a memory location. These differences are then
summed to produce a word result in the lower 16-bit field, and the upper
three words are set to zero.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)