Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-23
Assembly/Compiler Coding Rule 6. (H impact, M generality) Do not inline
a function if doing so increases the working set size beyond what will fit in the
trace cache.
Assembly/Compiler Coding Rule 7. (ML impact, ML generality) If there
are more than 16 nested calls and returns in rapid succession; consider
transforming the program with inline to reduce the call depth.
Assembly/Compiler Coding Rule 8. (ML impact, ML generality)
Favor
inlining small functions that contain branches with poor prediction rates. If a
branch misprediction results in a RETURN being prematurely predicted as
taken, a performance penalty may be incurred.
Assembly/Compiler Coding Rule 9. (L impact, L generality)
If the last
statement in a function is a call to another function, consider converting the
call to a jump. This will save the call/ return overhead as well as an entry in the
return stack buffer.
Assembly/Compiler Coding Rule 10. (M impact, L generality) Do not put
more than four branches in a 16-byte chunk.
Assembly/Compiler Coding Rule 11. (M impact, L generality) Do not put
more than two end loop branches in a 16-byte chunk.
Branch Type Selection
The default predicted target for indirect branches and calls is the
fall-through path. The fall-through prediction is overridden if and when
a hardware prediction is available for that branch. The predicted branch
target from branch prediction hardware for an indirect branch is the
previously executed branch target.
The default prediction to the fall-through path is only a significant issue
if no branch prediction is available, due to poor code locality or
pathological branch conflict problems. For indirect calls, predicting the
fall-through path is usually not an issue, since execution will likely
return to the instruction after the associated return.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)