Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-24
Placing data immediately following an indirect branch can cause a
performance problem. If the data consist of all zeros, it looks like a long
stream of adds to memory destinations, which can cause resource
conflicts and slow down branch recovery. Also, the data immediately
following indirect branches may appear as branches to the branch
predication hardware, which can branch off to execute other data pages.
This can lead to subsequent self-modifying code problems.
Assembly/Compiler Coding Rule 12. (M impact, L generality) When
indirect branches are present, try to put the most likely target of an indirect
branch immediately following the indirect branch. Alternatively, if indirect
branches are common but they cannot be predicted by branch prediction
hardware, then follow the indirect branch with a UD2 instruction, which will
stop the processor from decoding down the fall-through path.
Indirect branches resulting from code constructs, such as switch
statements, computed
GOTOs or calls through pointers, can jump to an
arbitrary number of locations. If the code sequence is such that the target
destination of a branch goes to the same address most of the time, then
the BTB will predict accurately most of the time. Since only one taken
(non-fall-through) target can be stored in the BTB, indirect branches
with multiple taken targets may have lower prediction rates.
The effective number of targets stored may be increased by introducing
additional conditional branches. Adding a conditional branch to a target
is fruitful if and only if:
• The branch direction is correlated with the branch history leading up
to that branch, that is, not just the last target, but how it got to this
branch.
• The source/target pair is common enough to warrant using the extra
branch prediction capacity. (This may increase the number of
overall branch mispredictions, while improving the misprediction of
indirect branches. The profitability is lower if the number of
mispredicting branches is very large).
User/Source Coding Rule 1. (M impact, L generality) If an indirect branch
has two or more common taken targets, and at least one of those targets are
correlated with branch history leading up to the branch, then convert the

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)