Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-17
demands only 50% of processor resources (based on idle history). The
processor frequency may be reduced by such multi-core unaware P-state
coordination, resulting in a performance anomaly. See Figure 9-5:
Software applications have a couple of choices to prevent this from
happening:
• Thread affinity management: A multi-threaded application can
enumerate processor topology and assign processor affinity to
application threads to prevent thread migration. This can work
around the issue of OS lacking multi-core aware P-state
coordination policy.
• Upgrade to an OS with multi-core aware P-state coordination
policy: Some newer OS releases may include multi-core aware
P-state coordination policy. The reader should consult with specific
OS vendors.
Multi-core Considerations for C-States
There are two aspects that impact C-states on multi-core processors:
1. Multi-core-unaware C-state coordination may not fully realize
power savings.
When each core in a multi-core processor meets the
requirements necessary to enter a different C-state type,
multi-core-unaware hardware coordination causes the physical
Figure 9-5 Thread Migration in a Multi-Core Processor
Core 1
Core 2
active
Idle
active
Idle

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)